[Intel-gfx] [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable

[Paulo Zanoni]

Hi

2012/10/31 Daniel Vetter <daniel.vetter at ffwll.ch>:
> Found in Bspec vol4h South Display Engine Registers [CPT, PPT],
> section "5.3.1  TRANS_CHICKEN_1—Transcoder Chicken Bits 1"
>
> v2: Make it compile.
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com> (v1)

R-B still applies... When I'm reviewing your patches I usually assume
they compile, so I didn't really try to compile this one :)

> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++++
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>  2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f1fe3a0..14851ab 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3803,6 +3803,10 @@
>  #define  TRANS_6BPC             (2<<5)
>  #define  TRANS_12BPC            (3<<5)
>
> +#define _TRANSA_CHICKEN1        0xf0060
> +#define _TRANSB_CHICKEN1        0xf1060
> +#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
> +#define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE     (1<<4)
>  #define _TRANSA_CHICKEN2        0xf0064
>  #define _TRANSB_CHICKEN2        0xf1064
>  #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3469fbd..a0e8f51 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3786,6 +3786,7 @@ static void ibx_init_clock_gating(struct drm_device *dev)
>  static void cpt_init_clock_gating(struct drm_device *dev)
>  {
>         struct drm_i915_private *dev_priv = dev->dev_private;
> +       int pipe;
>
>         /*
>          * On Ibex Peak and Cougar Point, we need to disable clock
> @@ -3795,6 +3796,11 @@ static void cpt_init_clock_gating(struct drm_device *dev)
>         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
>         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
>                    DPLS_EDP_PPS_FIX_DIS);
> +       /* WADP0ClockGatingDisable */
> +       for_each_pipe(pipe) {
> +               I915_WRITE(TRANS_CHICKEN1(pipe),
> +                          TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> +       }
>  }
>
>  void intel_init_clock_gating(struct drm_device *dev)
> --
> 1.7.11.4
>
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-- 
Paulo Zanoni