[Intel-gfx] [PATCH 1/9] drm/i915: move set_pll_edp to intel_dp.c

[Paulo Zanoni]

2012/11/5 Daniel Vetter <daniel.vetter at ffwll.ch>:
> Now that we enable the cpu edp pll in intel_dp->pre_enable and no
> longer in crtc_mode_set, we can also move the modeset part to the
> intel_dp->mode_set callback. Previously this was not possible because
> the encoder ->mode_set callbacks are called after the crtc mode set
> callback.
>
> v2: Rebase on top of copy&pasted hsw crtc_mode_set.
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>

Yay to all those magic unnamed registers....

Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 44 ------------------------------------
>  drivers/gpu/drm/i915/intel_dp.c      | 40 ++++++++++++++++++++++++++++++++
>  2 files changed, 40 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 27fc014..a221eb9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2297,43 +2297,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
>         return 0;
>  }
>
> -static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
> -{
> -       struct drm_device *dev = crtc->dev;
> -       struct drm_i915_private *dev_priv = dev->dev_private;
> -       u32 dpa_ctl;
> -
> -       DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
> -       dpa_ctl = I915_READ(DP_A);
> -       dpa_ctl &= ~DP_PLL_FREQ_MASK;
> -
> -       if (clock < 200000) {
> -               u32 temp;
> -               dpa_ctl |= DP_PLL_FREQ_160MHZ;
> -               /* workaround for 160Mhz:
> -                  1) program 0x4600c bits 15:0 = 0x8124
> -                  2) program 0x46010 bit 0 = 1
> -                  3) program 0x46034 bit 24 = 1
> -                  4) program 0x64000 bit 14 = 1
> -                  */
> -               temp = I915_READ(0x4600c);
> -               temp &= 0xffff0000;
> -               I915_WRITE(0x4600c, temp | 0x8124);
> -
> -               temp = I915_READ(0x46010);
> -               I915_WRITE(0x46010, temp | 1);
> -
> -               temp = I915_READ(0x46034);
> -               I915_WRITE(0x46034, temp | (1 << 24));
> -       } else {
> -               dpa_ctl |= DP_PLL_FREQ_270MHZ;
> -       }
> -       I915_WRITE(DP_A, dpa_ctl);
> -
> -       POSTING_READ(DP_A);
> -       udelay(500);
> -}
> -
>  static void intel_fdi_normal_train(struct drm_crtc *crtc)
>  {
>         struct drm_device *dev = crtc->dev;
> @@ -5433,9 +5396,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>
>         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
>
> -       if (is_cpu_edp)
> -               ironlake_set_pll_edp(crtc, adjusted_mode->clock);
> -
>         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
>
>         intel_wait_for_vblank(dev, pipe);
> @@ -5532,10 +5492,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
>         if (!is_dp || is_cpu_edp)
>                 ironlake_set_m_n(crtc, mode, adjusted_mode);
>
> -       if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> -               if (is_cpu_edp)
> -                       ironlake_set_pll_edp(crtc, adjusted_mode->clock);
> -
>         haswell_set_pipeconf(crtc, adjusted_mode, dither);
>
>         /* Set up the display plane register */
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 34ac746..e5f496b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -851,6 +851,43 @@ void intel_dp_init_link_config(struct intel_dp *intel_dp)
>         }
>  }
>
> +static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
> +{
> +       struct drm_device *dev = crtc->dev;
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +       u32 dpa_ctl;
> +
> +       DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
> +       dpa_ctl = I915_READ(DP_A);
> +       dpa_ctl &= ~DP_PLL_FREQ_MASK;
> +
> +       if (clock < 200000) {
> +               u32 temp;
> +               dpa_ctl |= DP_PLL_FREQ_160MHZ;
> +               /* workaround for 160Mhz:
> +                  1) program 0x4600c bits 15:0 = 0x8124
> +                  2) program 0x46010 bit 0 = 1
> +                  3) program 0x46034 bit 24 = 1
> +                  4) program 0x64000 bit 14 = 1
> +                  */
> +               temp = I915_READ(0x4600c);
> +               temp &= 0xffff0000;
> +               I915_WRITE(0x4600c, temp | 0x8124);
> +
> +               temp = I915_READ(0x46010);
> +               I915_WRITE(0x46010, temp | 1);
> +
> +               temp = I915_READ(0x46034);
> +               I915_WRITE(0x46034, temp | (1 << 24));
> +       } else {
> +               dpa_ctl |= DP_PLL_FREQ_270MHZ;
> +       }
> +       I915_WRITE(DP_A, dpa_ctl);
> +
> +       POSTING_READ(DP_A);
> +       udelay(500);
> +}
> +
>  static void
>  intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
>                   struct drm_display_mode *adjusted_mode)
> @@ -950,6 +987,9 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
>         } else {
>                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
>         }
> +
> +       if (is_cpu_edp(intel_dp))
> +               ironlake_set_pll_edp(crtc, adjusted_mode->clock);
>  }
>
>  #define IDLE_ON_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
> --
> 1.7.11.7
>
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-- 
Paulo Zanoni