[Intel-gfx] [PATCH 2/9] drm/i915: rip out pre-production ilk cpu edp w/a

[Paulo Zanoni]

Hi

2012/11/5 Daniel Vetter <daniel.vetter at ffwll.ch>:
> While reading docs I've noticed that this special workaround to select
> the 1.6 GHz DP clock only applies to pre-production ilk machines.
> Since the registers we're touching here are rather undocumented and
> might be harmful on later chips, rip it out.
>
> For the Bspec reference of this w/a look in "vol4g CPU Display
> Registers [DevILK]", Section 4.1.7.1 "DP_A—DisplayPort A
> Control Register", "DP_PLL_Frequency_Select".
>
> v2: Keep a debug message as a hint in case something regresses.
> Requested by Chris Wilson.
>
> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>

Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 21 +++++----------------
>  1 file changed, 5 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e5f496b..b2aa666 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -862,26 +862,15 @@ static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
>         dpa_ctl &= ~DP_PLL_FREQ_MASK;
>
>         if (clock < 200000) {
> -               u32 temp;
> +               /* For a long time we've carried around a ILK-DevA w/a for the
> +                * 160MHz clock. If we're really unlucky, it's still required.
> +                */

And if we're lucky, this fixes bugs :)

> +               DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
>                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
> -               /* workaround for 160Mhz:
> -                  1) program 0x4600c bits 15:0 = 0x8124
> -                  2) program 0x46010 bit 0 = 1
> -                  3) program 0x46034 bit 24 = 1
> -                  4) program 0x64000 bit 14 = 1
> -                  */
> -               temp = I915_READ(0x4600c);
> -               temp &= 0xffff0000;
> -               I915_WRITE(0x4600c, temp | 0x8124);
> -
> -               temp = I915_READ(0x46010);
> -               I915_WRITE(0x46010, temp | 1);
> -
> -               temp = I915_READ(0x46034);
> -               I915_WRITE(0x46034, temp | (1 << 24));
>         } else {
>                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
>         }
> +
>         I915_WRITE(DP_A, dpa_ctl);
>
>         POSTING_READ(DP_A);
> --
> 1.7.11.7
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni