[Intel-gfx] [PATCH 1/2] drm/i915: Don't allow ring tail to reach the same cacheline as head

[Ville Syrjälä]

On Mon, Nov 26, 2012 at 04:28:33PM +0000, Chris Wilson wrote:
> On Mon, 26 Nov 2012 14:48:18 +0200, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > According to BSpec the ring head and tail pointers must not be
> > on the same cacheline when head > tail. The easiest way to enforce
> > this is to reduce the reported ring space.
> 
> I'm going to admit blindness because I don't see that warning in the
> gen2-gen7 bspecs. Can you please give chapter and verse, and check to
> see if there is a rationale?

It's always the last thing in the section titled 'Ring Buffer Use'. I
believe it's present in all the pre-snb internal bspecs, and it's also
in all the public docs. I can't find it in the internal snb+ bspec but
then again those don't seem to include the relevant chapter at all.

Of course I can't be sure if it's a valid issue, or just something that
got faithfully copypasted from one document to the next.

-- 
Ville Syrjälä
Intel OTC