[Intel-gfx] [PATCH] drm/i915: Fix pte updates in ggtt clear range

[Chris Wilson]

On Mon, 26 Nov 2012 21:52:54 -0800, Ben Widawsky <ben at bwidawsk.net> wrote:
> This bug was introduced by me:
> commit e76e9aebcdbfebae8f4cd147e3c0f800d36e97f3
> Author: Ben Widawsky <ben at bwidawsk.net>
> Date:   Sun Nov 4 09:21:27 2012 -0800
> 
>     drm/i915: Stop using AGP layer for GEN6+
> 
> The existing code uses memset_io which follows memset semantics in only
> guaranteeing a write of individual bytes. Since a PTE entry is 4 bytes,
> this can only be correct if the scratch page address is 0.

Gah. Wasn't there an iowrite32_rep?
 
> This caused unsightly errors when we clear the range at load time,
> though I'm not really sure what the heck is referencing that memory
> anyway. I caught this is because I believe we have some other bug where
> the display is doing reads of memory we feel should be cleared (or we
> are relying on scratch pages to be a specific value).

That's just because we are no longer disabling outputs before updating
the GTT and hence continue to scanout from the BIOS fb during module
load. It's a regression that we'll be able to finally fix properly with
fastboot - though that will not be without its downsides either.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre