[Intel-gfx] [PATCH] drm/i915: Fix pte updates in ggtt clear range

[Chris Wilson]

On Tue, 27 Nov 2012 08:32:57 -0800, Ben Widawsky <ben at bwidawsk.net> wrote:
> On Tue, 27 Nov 2012 08:22:01 +0000
> Chris Wilson <chris at chris-wilson.co.uk> wrote:
> 
> > On Mon, 26 Nov 2012 21:52:54 -0800, Ben Widawsky <ben at bwidawsk.net>
> > wrote:
> > > This bug was introduced by me:
> > > commit e76e9aebcdbfebae8f4cd147e3c0f800d36e97f3
> > > Author: Ben Widawsky <ben at bwidawsk.net>
> > > Date:   Sun Nov 4 09:21:27 2012 -0800
> > > 
> > >     drm/i915: Stop using AGP layer for GEN6+
> > > 
> > > The existing code uses memset_io which follows memset semantics in
> > > only guaranteeing a write of individual bytes. Since a PTE entry is
> > > 4 bytes, this can only be correct if the scratch page address is 0.
> > 
> > Gah. Wasn't there an iowrite32_rep?
> 
> And you would hope it does what you want... but it seems like just a
> memcpy of dword sized chunks.

I feel suitably embarassed at missing it the first time, especially as
we've had similar conversations in the past.

Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre