[Intel-gfx] [PATCH v2 1/4] drm/i915: Don't allow ring tail to reach the same cacheline as head

[Ville Syrjälä]

On Wed, Nov 28, 2012 at 09:45:46PM +0100, Daniel Vetter wrote:
> On Tue, Nov 27, 2012 at 08:34:55PM +0200, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > From BSpec:
> > "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
> > cacheline, the Head Pointer must not be greater than the Tail
> > Pointer."
> > 
> > The easiest way to enforce this is to reduce the reported ring space.
> > 
> > References:
> > Gen2 BSpec "1. Programming Environment" / "1.4.4.6 Ring Buffer Use"
> > Gen3 BSpec "vol1c Memory Interface Functions" / "2.3.4.5 Ring Buffer Use"
> > Gen4+ BSpec "vol1c Memory Interface and Command Stream" / "5.3.4.5 Ring Buffer Use"
> > 
> > v2: Include the exact BSpec references in the description
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
> 
> Another small bikeshed for this one: Less magic numbers with
> 
> #define RING_FREE_SPACE 64

Can do. And since the number will only appear in one place, I think
I'll stick the BSpec references into a comment above it.

-- 
Ville Syrjälä
Intel OTC