[Intel-gfx] [PATCH] drm/i915: optimize ilk/snb irq handler

[Chris Wilson]

On Fri, 30 Nov 2012 11:24:50 +0100, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> We only need to read/write the south interrupt register if the
> corresponding bit is set in the north master interrupt register.
> Noticed while reading our interrupt handling code.
> 
> Same optimization has already been applied on ivb in
> 
> commit 0e43406bcc1868a316eea6012a0a09d992c53521
> Author: Chris Wilson <chris at chris-wilson.co.uk>
> Date:   Wed May 9 21:45:44 2012 +0100
> 
>     drm/i915: Simplify interrupt processing for IvyBridge
> 
>     We can take advantage that the PCH_IIR is a subordinate register to
>     reduce one of the required IIR reads, and that we only need to clear
>     interrupts handled to reduce the writes. And by simply tidying the code
>     we can reduce the line count and hopefully make it more readable.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre