[Intel-gfx] [PATCH 6/9] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB and VLV
Lespiau, Damien
damien.lespiau at intel.com
Mon Oct 1 18:57:14 CEST 2012
On Wed, Sep 19, 2012 at 9:29 PM, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> Workaround for dual port PS dispatch on GT1.
>
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e570aea..e863973 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4249,6 +4249,10 @@
> #define GEN7_L3LOG_BASE 0xB070
> #define GEN7_L3LOG_SIZE 0x80
>
> +#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
> +#define GEN7_HALF_SLICE_CHICKEN1_IVB 0xf100
> +#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
> +
> #define G4X_AUD_VID_DID 0x62020
> #define INTEL_AUDIO_DEVCL 0x808629FB
> #define INTEL_AUDIO_DEVBLC 0x80862801
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 372a398..f860cdd 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3537,6 +3537,17 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> CHICKEN3_DGMG_DONE_FIX_DISABLE);
>
> + /* WaDisablePSDDualDispatchEnable */
> + if (dev->pci_device == 0x0156 ||
> + dev->pci_device == 0x0152)
> + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> + I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> + else
> + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB,
> + I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> +
It looks like we don't need to force the single port dispatch on IVB
GT2 devices, maybe just drop the else then?
0x015a is also a GT1 device that seems to be missing from the if. I
guess it'd be nice to have an IS_IVB_GT1() macro there.
Other than those 2 points the rest looks good to me:
Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>
--
Damien
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