[Intel-gfx] [PATCH 05/12] drm/i915: implement WaGTEnableMiFlush on VLV

[Jesse Barnes]

We don't generally use MI_FLUSH these days, but this bit may affect
other flushing logic, so set it to be safe.

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 984a0c5..1718c54 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -512,6 +512,9 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 			I915_WRITE(GFX_MODE_GEN7,
 				   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 				   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
+		if (IS_VALLEYVIEW(dev))
+			I915_WRITE(MI_MODE, I915_READ(MI_MODE) |
+				   _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE));
 	}
 
 	if (INTEL_INFO(dev)->gen >= 5) {
-- 
1.7.9.5