[Intel-gfx] [PATCH 01/12] drm/i915: add more clock gating regs for gen7, make sure writes happen

[Ben Widawsky]

On Tue,  2 Oct 2012 17:43:35 -0500
Jesse Barnes <jbarnes at virtuousgeek.org> wrote:

> Add a few regs needed for various clock gating init purposes and make
> sure they don't fall into the display offset range on VLV.
> 
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |   17 +++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h |   11 +++++++++++
>  2 files changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c index a7837e5..205f61c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1128,6 +1128,23 @@ static bool IS_DISPLAYREG(u32 reg)
>  	if (reg == GEN6_GDRST)
>  		return false;
>  
> +	switch (reg) {
> +	case _3D_CHICKEN3:
> +	case IVB_CHICKEN3:
> +	case GEN7_HALF_SLICE_CHICKEN1:
> +	case GEN7_COMMON_SLICE_CHICKEN1:
> +	case GEN7_L3CNTLREG1:
> +	case GEN7_L3_CHICKEN_MODE_REGISTER:
> +	case GEN7_ROW_CHICKEN2:
> +	case GEN7_L3SQCREG4:
> +	case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
> +	case GEN6_MBCTL:
> +	case GEN6_UCGCTL2:
> +	case GEN7_UCGCTL4:
> +		return false;
> +	default:
> +		break;
> +	}
>  	return true;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index a828e90..7d133a1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -544,6 +544,8 @@
>  #define IIR		0x020a4
>  #define IMR		0x020a8
>  #define ISR		0x020ac
> +#define VLV_GUNIT_CLOCK_GATE	0x182060
> +#define   GCFG_DIS		(1<<8)
>  #define VLV_IIR_RW	0x182084
>  #define VLV_IER		0x1820a0
>  #define VLV_IIR		0x1820a4

This hunk doesn't really belong here, but not a big deal for me.

> @@ -4244,6 +4246,15 @@
>  #define GEN7_L3LOG_BASE			0xB070
>  #define GEN7_L3LOG_SIZE			0x80
>  
> +#define GEN7_HALF_SLICE_CHICKEN1	0xe100 /* IVB GT1 + VLV */
> +#define GEN7_HALF_SLICE_CHICKEN1_IVB	0xf100
> +#define   GEN7_MAX_PS_THREAD_DEP		(8<<12)
> +#define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE	(1<<3)
> +
> +#define GEN7_ROW_CHICKEN2		0xe4f4
> +#define GEN7_ROW_CHICKEN2_GT2		0xf4f4
> +#define   DOP_CLOCK_GATING_DISABLE	(1<<0)
> +
>  #define G4X_AUD_VID_DID			0x62020
>  #define INTEL_AUDIO_DEVCL		0x808629FB
>  #define INTEL_AUDIO_DEVBLC		0x80862801



-- 
Ben Widawsky, Intel Open Source Technology Center