[Intel-gfx] [PATCH 04/12] drm/i915: implement WaForceL3Serialization on VLV and IVB

[Ben Widawsky]

On Tue,  2 Oct 2012 17:43:38 -0500
Jesse Barnes <jbarnes at virtuousgeek.org> wrote:

> References: https://bugs.freedesktop.org/show_bug.cgi?id=50250
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>


> ---
>  drivers/gpu/drm/i915/i915_reg.h |    3 +++
>  drivers/gpu/drm/i915/intel_pm.c |    8 ++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3b75052..c75539b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3448,6 +3448,9 @@
>  #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
>  #define  GEN7_WA_DOP_CLOCK_GATING_DISABLE			0x08000000
>  
> +#define GEN7_L3SQCREG4				0xb034
> +#define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
> +
>  /* WaCatErrorRejectionIssue */
>  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
>  #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6be5910..0659317 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3549,6 +3549,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_ROW_CHICKEN2,
>  		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>  
> +	/* WaForceL3Serialization */
> +	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> +		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> +
>  	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
>  	 * gating disable must be set.  Failure to set it results in
>  	 * flickering pixels due to Z write ordering failures after
> @@ -3623,6 +3627,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_ROW_CHICKEN2,
>  		   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>  
> +	/* WaForceL3Serialization */
> +	I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
> +		   ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
> +
>  	/* This is required by WaCatErrorRejectionIssue */
>  	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>  		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |



-- 
Ben Widawsky, Intel Open Source Technology Center