[Intel-gfx] [PATCH 08/12] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB

[Ben Widawsky]

On Tue, 2 Oct 2012 16:51:39 -0700
Ben Widawsky <ben at bwidawsk.net> wrote:

> On Tue,  2 Oct 2012 17:43:42 -0500
> Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> 
> > Workaround for dual port PS dispatch on GT1.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c |   10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 400dd05..ce8d7b2 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3541,6 +3541,16 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> >  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> >  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
> >  
> > +	/* WaDisablePSDDualDispatchEnable */
> > +	if (IS_MOBILE(dev))
> > +		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> > +			   I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> > +			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> > +	else
> > +		I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB,
> > +			   I915_READ(GEN7_HALF_SLICE_CHICKEN1) |
> > +			   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> > +
> >  	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
> >  	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> >  		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
> 
> Seems like we need this on VLV too. Also, I can't find this register in
> the bspec, which is annoying - but I see the w/a.
> 

Also IS_MOBILE should be IS_GT1


-- 
Ben Widawsky, Intel Open Source Technology Center