[Intel-gfx] [PATCH 1/4] drm/i915: Remove duplicate cache workaround

[Ben Widawsky]

This is already achieved in init_clock gating, and is probably the
result of a bad merge from Daniel. I'm too tired to bet on him making a
mistake though.

CC: Daniel Vetter <daniel.vetter at ffwll.ch>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 984a0c5..625a348 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -521,14 +521,6 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 	}
 
 	if (IS_GEN6(dev)) {
-		/* From the Sandybridge PRM, volume 1 part 3, page 24:
-		 * "If this bit is set, STCunit will have LRA as replacement
-		 *  policy. [...] This bit must be reset.  LRA replacement
-		 *  policy is not supported."
-		 */
-		I915_WRITE(CACHE_MODE_0,
-			   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
-
 		/* This is not explicitly set for GEN6, so read the register.
 		 * see intel_ring_mi_set_context() for why we care.
 		 * TODO: consider explicitly setting the bit for GEN5
-- 
1.7.12.2