[Intel-gfx] [PATCH 10/12] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op

[Daniel Vetter]

On Wed, Oct 03, 2012 at 09:20:20AM +0200, Daniel Vetter wrote:
> On Tue, Oct 02, 2012 at 05:14:53PM -0700, Ben Widawsky wrote:
> > s/MI_FLUSH_SW/MI_FLUSH_DW/
> 
> Applied, with spelling fixed. Thanks for patch&review.

This hard-hangs my snb here when X starts (so probably on the very first
batch). Impressive!

I've dropped this one from -fixes. And since no one piped up that the
other w/a patches fix anything, I've moved those two I've merged already
to dinq.

Totally unrelated, I think I'll instate harsher rules for w/a patches:
1. w/a patches only go in through -fixes if they indeed fix an issue we
(or a bug reporter) can reproduce.
2. w/a patches need testcases, too. Either a register check added to i-g-t
or if it's a runtime thing, a runtime assert at a nice place (where
feasible, ofc).
3. I'll randomly stall patches to bring 2. up to par for existing
workarounds.

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch