[Intel-gfx] [PATCH 4/4] drm/i915: Fix GT_MODE default value

[Daniel Vetter]

On Wed, Oct 03, 2012 at 07:34:24PM -0700, Ben Widawsky wrote:
> I can't even find how I figured this might be needed anymore. But sure
> enough, the value I'm reading back on platforms doesn't match what the
> docs recommends.
> 
> It seemed to fix Chris' GT1 in limited testing as well.
> 
> Tested-by: Chris Wilson <chris at chris-wilson.co.uk>

Merged to -fixes, with the missing sob line forged.
-Daniel
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 37e62e0..4c1f461 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -531,6 +531,9 @@
>  # define VS_TIMER_DISPATCH				(1 << 6)
>  # define MI_FLUSH_ENABLE				(1 << 12)
>  
> +#define GEN6_GT_MODE	0x20d0
> +#define   GEN6_GT_MODE_HI	(1 << 9)
> +
>  #define GFX_MODE	0x02520
>  #define GFX_MODE_GEN7	0x0229c
>  #define RING_MODE_GEN7(ring)	((ring)->mmio_base+0x29c)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8aafa45..e0574f9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3446,6 +3446,11 @@ static void gen6_init_clock_gating(struct drm_device *dev)
>  			   DISPPLANE_TRICKLE_FEED_DISABLE);
>  		intel_flush_display_plane(dev_priv, pipe);
>  	}
> +
> +	/* The default value should be 0x200 according to docs, but the two
> +	 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
> +	I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
> +	I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
>  }
>  
>  static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
> -- 
> 1.7.12.2
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch