[Intel-gfx] [PATCH 02/14] drm/i915: add intel_ddi_set_pipe_settings

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

In theory, all the DDI pipe settings should be set here, including
timing and M/N registers. For now, let's just set the DP MSA
attributes.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 10 ++++++++++
 drivers/gpu/drm/i915/intel_ddi.c     | 34 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |  4 +++-
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 4 files changed, 48 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8200c31..7ca8b7d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4533,6 +4533,16 @@
 #define  PIPE_CLK_SEL_DISABLED		(0x0<<29)
 #define  PIPE_CLK_SEL_PORT(x)		((x+1)<<29)
 
+#define _PIPEA_MSA_MISC			0x60410
+#define _PIPEB_MSA_MISC			0x61410
+#define PIPE_MSA_MISC(pipe) _PIPE(pipe, _PIPEA_MSA_MISC, _PIPEB_MSA_MISC)
+#define  PIPE_MSA_SYNC_CLK		(1<<0)
+#define  PIPE_MSA_6_BPC			(0<<5)
+#define  PIPE_MSA_8_BPC			(1<<5)
+#define  PIPE_MSA_10_BPC		(2<<5)
+#define  PIPE_MSA_12_BPC		(3<<5)
+#define  PIPE_MSA_16_BPC		(3<<5)
+
 /* LCPLL Control */
 #define LCPLL_CTL			0x130040
 #define  LCPLL_PLL_DISABLE		(1<<31)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9659c227..e58df71 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -827,6 +827,40 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
 	return true;
 }
 
+void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
+	enum pipe pipe = intel_crtc->pipe;
+	int type = intel_encoder->type;
+	uint32_t temp;
+
+	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
+
+		temp = PIPE_MSA_SYNC_CLK;
+		switch (intel_crtc->bpp) {
+		case 18:
+			temp |= PIPE_MSA_6_BPC;
+			break;
+		case 24:
+			temp |= PIPE_MSA_8_BPC;
+			break;
+		case 30:
+			temp |= PIPE_MSA_10_BPC;
+			break;
+		case 36:
+			temp |= PIPE_MSA_12_BPC;
+			break;
+		default:
+			temp |= PIPE_MSA_8_BPC;
+			WARN(1, "%d bpp unsupported by pipe DDI function\n",
+			     intel_crtc->bpp);
+		}
+		I915_WRITE(PIPE_MSA_MISC(pipe), temp);
+	}
+}
+
 void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 705ed80..f48986b9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3218,8 +3218,10 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	 */
 	intel_crtc_load_lut(crtc);
 
-	if (IS_HASWELL(dev))
+	if (IS_HASWELL(dev)) {
+		intel_ddi_set_pipe_settings(crtc);
 		intel_ddi_enable_pipe_func(crtc);
+	}
 
 	intel_enable_pipe(dev_priv, pipe, is_pch_port);
 	intel_enable_plane(dev_priv, plane, pipe);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7e1e670..ed75a36 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -597,5 +597,6 @@ extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
 extern void intel_ddi_pre_enable(struct intel_encoder *intel_encoder);
 extern void intel_ddi_post_disable(struct intel_encoder *intel_encoder);
 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
+extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 
 #endif /* __INTEL_DRV_H__ */
-- 
1.7.11.4