[Intel-gfx] [PATCH 3/4] drm/i915: ILK also needs that last fix

[Daniel Vetter]

On Wed, Oct 03, 2012 at 07:34:23PM -0700, Ben Widawsky wrote:
> That fix was the disable render deptch cache pipeline flush
> 
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>

I've stumbled over the same one, but my docs here suggest i965g/gm45 need
it, too:

http://cgit.freedesktop.org/~danvet/drm/commit/?h=ilk-wa-pile&id=37c4c82b8cdbcf5adccad97f0b45747ba37ed659

Have you checked whether we don't need this on ivb/vlv/hsw, too?

Also, for w/a patches based on the vpg w/a database, please include the
vpg w/a name tag both in the commit message and in a code comment
somewhere.
-Daniel
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f1800ca..8aafa45 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3338,6 +3338,8 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(WM2_LP_ILK, 0);
>  	I915_WRITE(WM1_LP_ILK, 0);
>  
> +	I915_WRITE(CACHE_MODE_0,
> +		   _MASKED_BIT_ENABLE(CM0_RC_PIPELINE_FLUSH_DISABLE));
>  	/*
>  	 * Based on the document from hardware guys the following bits
>  	 * should be set unconditionally in order to enable FBC.
> -- 
> 1.7.12.2
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch