[Intel-gfx] [PATCH 06/14] drm/i915: add basic Haswell DP link train bits
Jani Nikula
jani.nikula at linux.intel.com
Tue Oct 16 13:47:02 CEST 2012
On Mon, 15 Oct 2012, Paulo Zanoni <przanoni at gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> Previously, the DP register was used for everything. On Haswell, it
> was split into DDI_BUF_CTL (which is the new intel_dp->DP register)
> and DP_TP_CTL.
>
> The logic behind this patch is based on a patch written by Shobhit
> Kumar, but the way the code was written is very different.
>
> Credits-to: Shobhit Kumar <shobhit.kumar at intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++
> drivers/gpu/drm/i915/intel_dp.c | 104 +++++++++++++++++++++++++++++++++++++---
> 2 files changed, 102 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7ca8b7d..68ce163 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4426,12 +4426,16 @@
> #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
> #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
> #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
> +#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
> +#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
> #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
> +#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
>
> /* DisplayPort Transport Status */
> #define DP_TP_STATUS_A 0x64044
> #define DP_TP_STATUS_B 0x64144
> #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
> +#define DP_TP_STATUS_IDLE_DONE (1<<25)
> #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
>
> /* DDI Buffer Control */
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3fa71cd..b10f35b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1476,7 +1476,19 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> {
> struct drm_device *dev = intel_dp->base.base.dev;
>
> - if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> + if (IS_HASWELL(dev)) {
> + switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> + case DP_TRAIN_VOLTAGE_SWING_400:
> + return DP_TRAIN_PRE_EMPHASIS_9_5;
> + case DP_TRAIN_VOLTAGE_SWING_600:
> + return DP_TRAIN_PRE_EMPHASIS_6;
> + case DP_TRAIN_VOLTAGE_SWING_800:
> + return DP_TRAIN_PRE_EMPHASIS_3_5;
> + case DP_TRAIN_VOLTAGE_SWING_1200:
> + default:
> + return DP_TRAIN_PRE_EMPHASIS_0;
> + }
> + } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_400:
> return DP_TRAIN_PRE_EMPHASIS_6;
> @@ -1630,6 +1642,40 @@ intel_gen7_edp_signal_levels(uint8_t train_set)
> }
> }
>
> +/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
> +static uint32_t
> +intel_dp_signal_levels_hsw(uint8_t train_set)
> +{
> + int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> + DP_TRAIN_PRE_EMPHASIS_MASK);
> + switch (signal_levels) {
> + case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
> + return DDI_BUF_EMP_400MV_0DB_HSW;
> + case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
> + return DDI_BUF_EMP_400MV_3_5DB_HSW;
> + case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
> + return DDI_BUF_EMP_400MV_6DB_HSW;
> + case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
> + return DDI_BUF_EMP_400MV_9_5DB_HSW;
> +
> + case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
> + return DDI_BUF_EMP_600MV_0DB_HSW;
> + case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
> + return DDI_BUF_EMP_600MV_3_5DB_HSW;
> + case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
> + return DDI_BUF_EMP_600MV_6DB_HSW;
> +
> + case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
> + return DDI_BUF_EMP_800MV_0DB_HSW;
> + case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
> + return DDI_BUF_EMP_800MV_3_5DB_HSW;
> + default:
> + DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
> + "0x%x\n", signal_levels);
> + return DDI_BUF_EMP_400MV_0DB_HSW;
> + }
> +}
> +
> static uint8_t
> intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
> int lane)
> @@ -1686,8 +1732,44 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> struct drm_device *dev = intel_dp->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> int ret;
> + uint32_t temp;
>
> - if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
> + if (IS_HASWELL(dev)) {
> + temp = I915_READ(DP_TP_CTL(intel_dp->port));
> +
> + if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
> + temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
> + else
> + temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
> +
> + temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> + switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> + case DP_TRAINING_PATTERN_DISABLE:
> + temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
> + I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
> +
> + if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
> + DP_TP_STATUS_IDLE_DONE) == 0, 1))
Shouldn't this wait for DP_TP_STATUS_IDLE_DONE to be set?
Otherwise,
Reviewed-by: Jani Nikula <jani.nikula at intel.com>
> + DRM_ERROR("Timed out waiting for DP idle patterns\n");
> +
> + temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> + temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
> +
> + break;
> + case DP_TRAINING_PATTERN_1:
> + temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
> + break;
> + case DP_TRAINING_PATTERN_2:
> + temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
> + break;
> + case DP_TRAINING_PATTERN_3:
> + temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
> + break;
> + }
> + I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
> +
> + } else if (HAS_PCH_CPT(dev) &&
> + (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
> dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
>
> switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> @@ -1774,8 +1856,11 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> uint8_t link_status[DP_LINK_STATUS_SIZE];
> uint32_t signal_levels;
>
> -
> - if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> + if (IS_HASWELL(dev)) {
> + signal_levels = intel_dp_signal_levels_hsw(
> + intel_dp->train_set[0]);
> + DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
> + } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
> DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
> } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> @@ -1783,9 +1868,10 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
> } else {
> signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
> - DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
> DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
> }
> + DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
> + signal_levels);
>
> if (!intel_dp_set_link_train(intel_dp, DP,
> DP_TRAINING_PATTERN_1 |
> @@ -1861,7 +1947,10 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> break;
> }
>
> - if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> + if (IS_HASWELL(dev)) {
> + signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
> + DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
> + } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
> signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
> DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
> } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
> @@ -1908,6 +1997,9 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> ++tries;
> }
>
> + if (channel_eq)
> + DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
> +
> intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
> }
>
> --
> 1.7.11.4
>
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