[Intel-gfx] bad panel power sequencing delays, disabling panel

[Daniel Vetter]

On Tue, Oct 16, 2012 at 6:10 PM, Daniel J Blueman <daniel at quora.org> wrote:
> [drm:intel_dp_init], cur t1_t3 0 t8 0 t9 0 t10 0 t11_t12 4000
> [drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0
> [drm:intel_dp_init], panel power up delay 21, power down delay 50,
> power cycle delay 400
> [drm:intel_dp_init], backlight on delay 5, off delay 5
> [drm:intel_dp_init], panel power sequencer register settings: PP_ON
> 0x40d20032, PP_OFF 0x1f40032, PP_DIV 0x186904
> [drm:intel_dp_i2c_init], i2c_init DPDDC-A
> [drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on
> [drm:ironlake_edp_panel_vdd_on], eDP VDD already on
> [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x514500c8
> [drm:intel_dp_i2c_aux_ch], aux_ch failed -110
>
> Notable, the nvidia DP init script executed fine; perhaps tracing the
> I2C access may be useful?

Hm, dp aux transfer don't work (this is the first one in the setup
sequence, so it's not an i2c over aux issue with the edid read). I
guess the mux is getting in the way. Dave, do you have an idea what's
still going wrong? panel power sequence is now operationl. For
reference, the wip patch series is at:
http://cgit.freedesktop.org/~danvet/drm/log/?h=for-pzanoni

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch