[Intel-gfx] [PATCH] drm/i915: flush system agent TLBs on SNB so we can WC map the PTEs

[Daniel Vetter]

On Tue, Oct 16, 2012 at 9:11 PM, Paulo Zanoni <przanoni at gmail.com> wrote:
> 2012/10/11 Jesse Barnes <jbarnes at virtuousgeek.org>:
>> I've only lightly tested this so far, but the corruption seems to be
>> gone if I write the GFX_FLSH_CNTL reg after binding an object.  This
>> register should control the TLB for the system agent, which is what CPU
>> mapped objects will go through.
>>
>> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
>>
>> diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
>> index 6ec0fff..95f0d4d 100644
>> --- a/drivers/char/agp/intel-agp.h
>> +++ b/drivers/char/agp/intel-agp.h
>> @@ -99,6 +99,9 @@
>>  #define GFX_FLSH_CNTL          0x2170 /* 915+ */
>>  #define GFX_FLSH_CNTL_VLV      0x101008
>>
>> +#define GFX_FLSH_CNTL          0x101008
>> +#define   GFX_FLSH_CNTL_EN     (1<<0)
>
> Notice that there's a redefinition of GFX_FLSH_CNTL with a different
> value just 3 lines above. We're probably fixing gen6+ and breaking
> gen5-

Yeah, Jesse needs to fix up this patch (or me, since it'll conflict
anyway with -fixes, so I need a backmerge first).

> We write 0 to this reg in some places, but I believe that shouldn't matter.

This is one of the magic registers we have: Read always returns 0, it
doesn't matter what you write into it, but something special happens
as a side-effect of writing to it. In this case we flush the cpu gtt
tlb. We have a few others of this kind.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch