[Intel-gfx] [PATCH 4/4] drm/i915: Review the memory barriers around CPU access to buffers

[Chris Wilson]

On Thu, 11 Oct 2012 12:52:15 -0700, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> On Tue,  9 Oct 2012 19:24:40 +0100
> Chris Wilson <chris at chris-wilson.co.uk> wrote:
> 
> > We need to treat the GPU core as a distinct processor and so apply the
> > same SMP memory barriers. In this case, in addition to flushing the
> > chipset cache, which is a no-op on LLC platforms, apply a write barrier
> > beforehand. And then when we invalidate the CPU cache, make sure the
> > memory is coherent (again this was a no-op on LLC platforms).
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > ---
> >  drivers/char/agp/intel-gtt.c    |    1 +
> >  drivers/gpu/drm/i915/i915_gem.c |    1 +
> >  2 files changed, 2 insertions(+)
> > 
> > diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> > index 8b0f6d19..1223128 100644
> > --- a/drivers/char/agp/intel-gtt.c
> > +++ b/drivers/char/agp/intel-gtt.c
> > @@ -1706,6 +1706,7 @@ EXPORT_SYMBOL(intel_gtt_get);
> >  
> >  void intel_gtt_chipset_flush(void)
> >  {
> > +	wmb();
> >  	if (intel_private.driver->chipset_flush)
> >  		intel_private.driver->chipset_flush();
> >  }
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index ed8d21a..b1ebb88 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -3528,6 +3528,7 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
> >  	/* Flush the CPU cache if it's still invalid. */
> >  	if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
> >  		i915_gem_clflush_object(obj);
> > +		mb(); /* in case the clflush above is optimised away */
> >  
> >  		obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
> >  	}
> 
> These need more comments too.
> 
> I think the first is to make sure any previous loads have completed
> before we start using the new object?  If so, don't we want reads to
> complete first too?

The flush is only used to make sure the writes written from the CPU hit
the cache and/or chipset buffers before we flush them from the chipset
buffer. Userspace is welcome to race read/writes between cores and the
GPU, and there is nothing we can do to prevent that without adopting a
strict coherency model.

Also note that in the past I have proposed this wmb() to fix some
observed incoherency in the cursor sprite: #21442.
 
> The second one looks unnecessary.  If the object isn't in the CPU
> domain, there should be no loads/stores against it right?

Just depends on the programming model between CPU/GPU. The barrier is
there to make sure all the writes into the shared cache from another
core (the gpu in this case) is complete before we begin our reads.
Assuming that the GPU behaves as another core...
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre