[Intel-gfx] [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

[Chris Wilson]

On Thu, 18 Oct 2012 13:07:18 -0500, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> "If ENABLED, PIPE_CONTROL command will flush the in flight data  written
> out by render engine to Global Observation point on flush done. Also
> Requires stall bit ([20] of DW1) set."

That quotation doesn't make sense in the context of TLB invalidation,
and the programming guide here very carefully avoids the mention of
requiring any stall bit set for the post-sync op of TLB invalidation.

Maybe quote chapter and verse as well?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre