[Intel-gfx] [PATCH 15/18] drm/i915: set the correct eDP aux channel clock divider on DDI

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>

On Tue, Oct 23, 2012 at 6:30 PM, Paulo Zanoni <przanoni at gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> The cdclk frequency is not always the same, so the value here should
> be adjusted to match it.
>
> Version 2: call intel_ddi_get_cdclk_freq instead of reading
> CDCLK_FREQ, because the register is just for earlier HW steppings.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 2 +-
>  drivers/gpu/drm/i915/intel_dp.c  | 4 +++-
>  drivers/gpu/drm/i915/intel_drv.h | 1 +
>  3 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 106c375..30b0db7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1239,7 +1239,7 @@ void intel_disable_ddi(struct intel_encoder *encoder)
>         /* This will be needed in the future, so leave it here for now */
>  }
>
> -static int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
> +int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
>  {
>         if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
>                 return 450;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f15ea22..6d30b2d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -370,7 +370,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>          * clock divider.
>          */
>         if (is_cpu_edp(intel_dp)) {
> -               if (IS_VALLEYVIEW(dev))
> +               if (IS_HASWELL(dev))
> +                       aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
> +               else if (IS_VALLEYVIEW(dev))
>                         aux_clock_divider = 100;
>                 else if (IS_GEN6(dev) || IS_GEN7(dev))
>                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 65927d9..c05e892 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -609,6 +609,7 @@ extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
>  extern void intel_ddi_mode_set(struct drm_encoder *encoder,
>                                 struct drm_display_mode *mode,
>                                 struct drm_display_mode *adjusted_mode);
> +extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
>  extern void intel_ddi_pll_init(struct drm_device *dev);
>  extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
>  extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
> --
> 1.7.11.4
>
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br