[Intel-gfx] [PATCH 07/10] drm/i915: Calculate correct stolen size for GEN7+

[Ben Widawsky]

On Thu, 25 Oct 2012 14:06:48 -0700
Jesse Barnes <jbarnes at virtuousgeek.org> wrote:

> On Mon, 22 Oct 2012 18:34:12 -0700
> Ben Widawsky <ben at bwidawsk.net> wrote:
> 
> > This bug existed in the old code, but was easier to fix here in the
> > rework. Unfortunately gen7 doesn't have a nice way to figure out the
> > size and we must use a lookup table.
> > 
> > Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> > ---
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +++++++++++++-
> >  drivers/gpu/drm/i915/i915_reg.h     |  2 ++
> >  2 files changed, 15 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 7d3ec42..16fe960 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -528,6 +528,15 @@ static inline unsigned int gen6_get_stolen_size(u16 snb_gmch_ctl)
> >  	return snb_gmch_ctl << 25; /* 32 MB units */
> >  }
> >  
> > +static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl)
> > +{
> > +	static const int stolen_decoder[] = {
> > +		0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
> > +	snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
> > +	snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
> > +	return stolen_decoder[snb_gmch_ctl] << 20;
> > +}
> > +
> >  int i915_gem_gtt_init(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -575,7 +584,10 @@ int i915_gem_gtt_init(struct drm_device *dev)
> >  	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
> >  	dev_priv->mm.gtt->gtt_total_entries =
> >  		gen6_get_total_gtt_size(snb_gmch_ctl) / sizeof(gtt_pte_t);
> > -	dev_priv->mm.gtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
> > +	if (INTEL_INFO(dev)->gen < 7)
> > +		dev_priv->mm.gtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
> > +	else
> > +		dev_priv->mm.gtt->stolen_size = gen7_get_stolen_size(snb_gmch_ctl);
> >  
> >  	ret = setup_scratch_page(dev);
> >  	if (ret)
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 10a6e9b..1d54328 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -45,6 +45,8 @@
> >  #define    SNB_GMCH_GGMS_MASK	0x3
> >  #define    SNB_GMCH_GMS_SHIFT   3 /* Graphics Mode Select */
> >  #define    SNB_GMCH_GMS_MASK    0x1f
> > +#define    IVB_GMCH_GMS_SHIFT   4
> > +#define    IVB_GMCH_GMS_MASK    0xf
> >  
> >  
> >  /* PCI config space */
> 
> Hm my docs say different.  Supposedly the size field starts at bit 3
> and is 5 bits wide, going up to 512M.  So just like SNB but with a
> bigger max.
> 

So we discussed this a bit on IRC. I think we decided to leave it as is?

-- 
Ben Widawsky, Intel Open Source Technology Center