[Intel-gfx] [PATCH] drm/i915: Fix sprite offset on HSW

[Paulo Zanoni]

Hi

2012/10/25 Damien Lespiau <damien.lespiau at gmail.com>:
> From: Damien Lespiau <damien.lespiau at intel.com>
>
> HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
> register.
>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h     |    3 +++
>  drivers/gpu/drm/i915/intel_sprite.c |   18 +++++++++++++-----
>  2 files changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index be22aeb..2a6c0b6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3187,6 +3187,7 @@
>  #define _SPRA_SURF             0x7029c
>  #define _SPRA_KEYMAX           0x702a0
>  #define _SPRA_TILEOFF          0x702a4
> +#define _SPRA_OFFSET           0x702a4
>  #define _SPRA_SCALE            0x70304
>  #define   SPRITE_SCALE_ENABLE  (1<<31)
>  #define   SPRITE_FILTER_MASK   (3<<29)
> @@ -3207,6 +3208,7 @@
>  #define _SPRB_SURF             0x7129c
>  #define _SPRB_KEYMAX           0x712a0
>  #define _SPRB_TILEOFF          0x712a4
> +#define _SPRB_OFFSET           0x712a4
>  #define _SPRB_SCALE            0x71304
>  #define _SPRB_GAMC             0x71400
>
> @@ -3220,6 +3222,7 @@
>  #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
>  #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
>  #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
> +#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
>  #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
>  #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 176c462..24b8231 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -127,13 +127,21 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
>
>         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
>         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
> -       if (obj->tiling_mode != I915_TILING_NONE) {
> -               I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
> +
> +       if (IS_HASWELL(dev)) {
> +               /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single
> +                * SPROFFSET register */
> +               I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
>         } else {
> -               unsigned long offset;
> +               if (obj->tiling_mode != I915_TILING_NONE) {
> +                       I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
> +               } else {
> +                       unsigned long offset;
>
> -               offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
> -               I915_WRITE(SPRLINOFF(pipe), offset);
> +                       offset = y * fb->pitches[0] +
> +                                x * (fb->bits_per_pixel / 8);
> +                       I915_WRITE(SPRLINOFF(pipe), offset);
> +               }

<bikeshed>
Doing "if (is_hsw) { code; } else if (obj->tiling_mode) { code; } else
{ code; }" would probably make reading the patch easier :)
But I don't really think you need to resend just because of this.
</bikeshed>

Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

I'd love to see the same fix for the "Primary Plane" registers since
this will get us rid of many "Unclaimed write" messages.

>         }
>         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
>         if (intel_plane->can_scale)
> --
> 1.7.7.5
>
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-- 
Paulo Zanoni