[Intel-gfx] [PATCH 2/9] drm/i915: Write the FDI RX TU size reg at the right time

[Paulo Zanoni]

2012/10/26 Daniel Vetter <daniel.vetter at ffwll.ch>:
> According to "Graphics BSpec: vol4g North Display Engine Registers [IVB],
> Display Mode Set Sequence" We need to write the TU size register
> of the fdi RX unit _before_ starting to train the link.

Well, we are still writing it before training the link, but it's
waaaaay before :)
But I agree with the patch, it makes the code look more like our mode
set sequence docs.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0261d18..6cc9cb9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2681,9 +2681,6 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
>         int pipe = intel_crtc->pipe;
>         u32 reg, temp;
>
> -       /* Write the TU size bits so error detection works */
> -       I915_WRITE(FDI_RX_TUSIZE1(pipe),
> -                  I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
>
>         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
>         reg = FDI_RX_CTL(pipe);
> @@ -2996,6 +2993,11 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>
>         assert_transcoder_disabled(dev_priv, pipe);
>
> +       /* Write the TU size bits before fdi link training, so that error
> +        * detection works. */
> +       I915_WRITE(FDI_RX_TUSIZE1(pipe),
> +                  I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
> +
>         /* For PCH output, training FDI link */
>         dev_priv->display.fdi_link_train(crtc);
>
> --
> 1.7.11.4
>
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-- 
Paulo Zanoni