[Intel-gfx] [PATCH 5/9] drm/i915: CPT/PPT pch dp transcoder workaround

[Paulo Zanoni]

2012/10/29 Daniel Vetter <daniel at ffwll.ch>:
> On Fri, Oct 26, 2012 at 12:21:11PM -0200, Paulo Zanoni wrote:
>> Hi
>>
>> 2012/10/26 Daniel Vetter <daniel.vetter at ffwll.ch>:
>> > We need to set the timing override chicken bit after fdi link training
>> > has completed and before we enable the dp transcoder. We also have to
>> > clear that bit again after disabling the pch dp transcoder.
>> >
>> > See "Graphics BSpec: vol4g North Display Engine Registers [IVB],
>> > Display Mode Set Sequence" and "Graphics BSpec: vol4h South Display
>> > Engine Registers [CPT, PPT], South Display Engine Transcoder and FDI
>> > Control, Transcoder Debug and DFT, TRANS_CHICKEN_2" bit 31:
>> >
>> > "Workaround : Enable the override prior to enabling the transcoder.
>> > Disable the override after disabling the transcoder."
>> >
>> > While at it, use the _PIPE macro for the other TRANS_DP register.
>>
>> What confuses me is that the bit name is actually "Autotrain TimingGen
>> Override" and after a quick check it seems we don't use autotrain.
>> Also, by looking at the IVB mode set sequence it seems Auto Train is
>> the *recommended* method since manual is listed as "testing only". So
>> I'm not sure if we need this code now, but it seems we could try to
>> implement the auto train...
>
> Well, us using manual fdi train is a different matter altogether. And
> since there's nothing in the docs indicating that we don't need this w/a
> if we don't do autotraining, I prefer to just stick it into the code.
>
> And Damien tried to do the auto training, but somehow it failed ...
>
>> Also, I'd move the code that sets/unsets the chicken bit to
>> intel_enable_transcoder/intel_disable_transcoder.
>
> According to my reading of the modeset sequence we need to do this after
> the fdi train is fully done, but before we enable the pch dp transcoder.

>From what I could understand your patch does the following:

Enable:
- Step 9.g (configure PCH timings)
- Apply workaround
- Step 9.h (configure TRANS_DP_CTL)
- Step 9.i (enable PCH transcoder)

Disable:
- Step 10.e (wait PCH transcoder off)
- Step 10.f (disable TRANS_DP_CTL)
- Apply workaround
- Step 10.g (disable transcoder DPLL)


My understand is that we should be doing:

Enable:
- Step 9.g (configure PCH timings)
- Step 9.h (configure TRANS_DP_CTL)
- Apply workaround
- Step 9.i (enable PCH transcoder)

Disable:
- Step 10.e (wait PCH transcoder off)
- Apply workaround
- Step 10.f (disable TRANS_DP_CTL)
- Step 10.g (disale transcoder DPLL)

The description of the chicken bit used in the workaround even says that:
"Workaround: Enable the override prior to enabling the transcoder.
Disable the override after disabling the transcoder".

That's why I said we should implement the workaround in
intel_enable_transcoder and intel_disable_transcoder: it matches the
register description and also matches what I understood from our mode
set sequence.


> So I think this is the right place, and I can't actually move it anyplace
> else. And since the pch dp transcoder is a cpt/ppt-only feature, it' fits
> rather naturally.
>
> Cheers, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



-- 
Paulo Zanoni