[Intel-gfx] [PATCH] drm/i915/tv: Use intel_flush_display_plane() to flush the primary plane
Paulo Zanoni
przanoni at gmail.com
Mon Oct 29 20:58:49 CET 2012
Hi
2012/10/29 Damien Lespiau <damien.lespiau at gmail.com>:
> From: Damien Lespiau <damien.lespiau at intel.com>
>
> Instead of writing to the DSP_ADDR ourselves. This will do the right
> thing on gen >= 4 as well.
>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
I hope this will allow us to close bugs...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> drivers/gpu/drm/i915/intel_tv.c | 7 ++-----
> 1 files changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
> index 62bb048..86d5c20 100644
> --- a/drivers/gpu/drm/i915/intel_tv.c
> +++ b/drivers/gpu/drm/i915/intel_tv.c
> @@ -1088,13 +1088,11 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
> int dspcntr_reg = DSPCNTR(intel_crtc->plane);
> int pipeconf = I915_READ(pipeconf_reg);
> int dspcntr = I915_READ(dspcntr_reg);
> - int dspbase_reg = DSPADDR(intel_crtc->plane);
> int xpos = 0x0, ypos = 0x0;
> unsigned int xsize, ysize;
> /* Pipe must be off here */
> I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
> - /* Flush the plane changes */
> - I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
> + intel_flush_display_plane(dev_priv, intel_crtc->plane);
>
> /* Wait for vblank for the disable to take effect */
> if (IS_GEN2(dev))
> @@ -1123,8 +1121,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
>
> I915_WRITE(pipeconf_reg, pipeconf);
> I915_WRITE(dspcntr_reg, dspcntr);
> - /* Flush the plane changes */
> - I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
> + intel_flush_display_plane(dev_priv, intel_crtc->plane);
> }
>
> j = 0;
> --
> 1.7.7.5
>
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--
Paulo Zanoni
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