[Intel-gfx] [PATCH 2/3] drm/i915: put ring frequency and turbo setup into a work queue v2

[Daniel Vetter]

On Tue, Oct 30, 2012 at 6:03 PM, Rodrigo Vivi <rodrigo.vivi at gmail.com> wrote:
> I was here trying to cheking init values and change forcewake set
> during init, etc and nothing was getting RC6 running after resume
> besides that msleep(50) workaround after setting CACHE_MODE_0...
>
> Now with your patch my RC6 is back to life after resume: RC6 35.8% :D
>
> Well, but when looking at BSPec I noticed that CACHE_MODE_0 is 0x02120
> only for SNB. For IVB+ is 0x7004 what is defined as CACHE_MODE_1 in
> our code.
> I'm afraid we are doing something wrong here.... or am I missing something?

This is the legacy register save/restore code for resume, which should
be burnt. On a big pyre. With gasoline. Really.

Cheers, Daniel

PS: Unfortunately it's a giant mess to review all the code paths and
make sure that we can disable a given register restore block for kms.
I've started, but it's slow-going (see the "dont save/restore * regs
for kms" patch series which is already merged). Patches _highly_
welcome.
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch