[Intel-gfx] [PATCH 6/9 v3] drm/i915: Stop using AGP layer for GEN6+

[Ben Widawsky]

On Wed, 31 Oct 2012 10:57:08 +0100
Daniel Vetter <daniel at ffwll.ch> wrote:

> On Sun, Oct 28, 2012 at 07:08:56PM -0700, Ben Widawsky wrote:
> > As a quick hack we make the old intel_gtt structure mutable so we
> > can fool a bunch of the existing code which depends on elements in
> > that data structure. We can/should try to remove this in a
> > subsequent patch.
> > 
> > This should preserve the old gtt init behavior which upon writing
> > these patches seems incorrect. The next patch will fix these things.
> > 
> > The one exception is VLV which doesn't have the preserved flush
> > control write behavior. Since we want to do that for all GEN6+
> > stuff, we'll handle that in a later patch. Mainstream VLV support
> > doesn't actually exist yet anyway.
> > 
> > v2: Update the comment to remove the "voodoo"
> > Check that the last pte written matches what we readback
> > 
> > v3: actually kill cache_level_to_agp_type since most of the flags
> > will dissapear in an upcoming patch
> > 
> > Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> 
> Just wanted to merge this entire pile, but then stumbled over a small
> thing: You can't kill the cache_level_to_agp_type stuff, since we now
> have different cache levels even on pre-gen6. Otherwise you'll break
> cacheable bos in SNA, which will anger Chris ;-)
> 
> Thanks, Daniel

Well, I'm not even going to go bother to figure out what
I830_PTE_SYSTEM_CACHED even means. I can still kill it and turn
it into a simple if statement in bind_object.

Chris left some other comments to address, so it needed a new version
anyway.

Thanks for the feedback.