[Intel-gfx] [PATCH 00/36] Haswell VGA fixes

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

Hi

As you may have noticed this is not "Haswell VGA enablement", but "Haswell VGA
fixes" since VGA is already enabled on Haswell. Even though it's enabled,
whenever I try to "xrandr --output VGA1 --auto" my machine hard hangs.

So what does this series fixes?
  - It makes our code follow the "mode set sequence for CRT" described in our
    documentation.
  - It makes my old VGA monitor work :)

What kind of problems remain?

  - I really don't know exactly what problems remain, but this series just does
    not touch the code that sets the PCH clocks and I'm sure that code is
    incomplete. We are probably still relying on the fact that the BIOS enables
    things for us. But since I didn't even touch that code and VGA works for me,
    I think we can address those problems in a later patch series.

How does the series fix the problems?

  - It forks some of the Ironlake PCH functions.
  - It makes all those forked functions aware of the fact that there's only one
    CPU transcoder and that CPU transcoder may be different from CPU pipe.
  - It changes a lot of things to make sure we follow the mode set sequence.

The number of patches may be scary, but each patch tries to be really small and
easy to review, so if you grab our "mode set sequence" document you'll be able
to review a lot of patches in just a few minutes :)

Cheers,
Paulo

Paulo Zanoni (36):
  drm/i915: don't set ADPA pipe select on LPT
  drm/i915: use intel_ddi_get_hw_state on CRT encoder too
  drm/i915: add lpt_pch_enable
  drm/i915: remove Haswell/LPT bits from ironlake_pch_enable
  drm/i915: remove ironlake bits from lpt_pch_enable
  drm/i915: train Haswell FDI at the right time
  drm/i915: use the right FDI_RX_CTL register on Haswell
  drm/i915: set the correct number of FDI lanes on Haswell
  drm/i915: don't rely on DDI_BUF_CTL previous values
  drm/i915: program the FDI RX TUSIZE register on hsw_fdi_link_train
  drm/i915: properly program FDI_RX_MISC pwrdn lane values on HSW
  drm/i915: wait only 35us for the FDI link training
  drm/i915: remove an useless indentation level on hsw_fdi_link_train
  drm/i915: disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE
  drm/i915: change Haswell FDI link training error messages
  drm/i915: try each voltage twice at hsw_fdi_link_train
  drm/i915: fix Haswell FDI link disable path
  drm/i915: don't write FDI_RX_TUSIZE on lpt_pch_enable
  drm/i915: rename intel_enable_pch_pll to ironlake_enable_pch_pll
  drm/i915: don't call ironlake_enable_pch_pll on lpt_pch_enable
  drm/i915: don't assert_panel_unlocked on LPT
  drm/i915: use the CPU and PCH transcoders on lpt_pch_enable
  drm/i915: rename intel_{en,dis}able_transcoder
  drm/i915: fork lpt version of ironlake_{en,dis}able_pch_transcoder
  drm/i915: remove Haswell code from ironlake_enable_pch_transcoder
  drm/i915: remove IBX code from lpt_enable_pch_transcoder
  drm/i915: don't assert_pch_pll_enabled on lpt_enable_pch_transcoder
  drm/i915: use CPU and PCH transcoders on lpt_enable_pch_transcoder
  drm/i915: use PIPECONF_INTERLACE_MASK_HSW on
    lpt_enable_pch_transcoder
  drm/i915: don't rely on previous values when setting LPT TRANSCONF
  drm/i915: don't assert_pch_ports_disabled on LPT
  drm/i915: use CPU and PCH transcoders on lpt_disable_pch_transcoder
  drm/i915: implement timing override workarounds on LPT
  drm/i915: don't intel_disable_pch_pll on Haswell/LPT
  drm/i915: don't limit Haswell CRT encoder to pipe A
  drm/i915: don't assert disabled FDI before disabling the FDI

 drivers/gpu/drm/i915/i915_reg.h      |  17 +++--
 drivers/gpu/drm/i915/intel_crt.c     |  14 ++--
 drivers/gpu/drm/i915/intel_ddi.c     | 134 +++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_display.c | 127 +++++++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_drv.h     |   4 +-
 5 files changed, 202 insertions(+), 94 deletions(-)

-- 
1.7.11.4