[Intel-gfx] [PATCH 32/36] drm/i915: use CPU and PCH transcoders on lpt_disable_pch_transcoder

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

... instead of "pipe", which is wrong.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7d858f8..ae22d4d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1766,22 +1766,20 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
 }
 
 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
-				       enum pipe pipe)
+				       enum transcoder cpu_transcoder)
 {
-	int reg;
 	u32 val;
 
 	/* FDI relies on the transcoder */
-	assert_fdi_tx_disabled(dev_priv, pipe);
-	assert_fdi_rx_disabled(dev_priv, pipe);
+	assert_fdi_tx_disabled(dev_priv, cpu_transcoder);
+	assert_fdi_rx_disabled(dev_priv, TRANSCODER_A);
 
-	reg = TRANSCONF(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(_TRANSACONF);
 	val &= ~TRANS_ENABLE;
-	I915_WRITE(reg, val);
+	I915_WRITE(_TRANSACONF, val);
 	/* wait for PCH transcoder off, transcoder state */
-	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
-		DRM_ERROR("failed to disable transcoder %d\n", pipe);
+	if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
+		DRM_ERROR("Failed to disable PCH transcoder\n");
 }
 
 /**
@@ -3589,7 +3587,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 			encoder->post_disable(encoder);
 
 	if (is_pch_port) {
-		lpt_disable_pch_transcoder(dev_priv, pipe);
+		lpt_disable_pch_transcoder(dev_priv, cpu_transcoder);
 		intel_disable_pch_pll(intel_crtc);
 		intel_ddi_fdi_disable(crtc);
 	}
-- 
1.7.11.4