[Intel-gfx] [PATCH 2/8] drm/i915: extract LVDS-specific code from ironlake_crtc_mode_set
Daniel Vetter
daniel at ffwll.ch
Wed Sep 12 15:56:05 CEST 2012
On Wed, Sep 12, 2012 at 10:06:30AM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> A next step would be to move this code to some of the encoder-specific
> callbacks. But really, moving the function away is certainly the first
> step.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
I have a slightly more ambitious version of this in my modeset-rework
branch - it also consolidates the lvds port enabling with the pre-pch code
and encapsulates it within a new encoder->pre_pll_enable callback. Since
this is part of a larger rework of how we handle clock settings that I'm
toying around with, I'd like to keep things as-is for now.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 37 ++---------------------------
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> drivers/gpu/drm/i915/intel_lvds.c | 43 ++++++++++++++++++++++++++++++++++
> 3 files changed, 48 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 244bce6..cf1e628 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4710,7 +4710,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> const intel_limit_t *limit;
> int ret;
> struct fdi_m_n m_n = {0};
> - u32 temp;
> int target_clock, pixel_multiplier, lane, link_bw, factor;
> unsigned int pipe_bpp;
> bool dither;
> @@ -4933,40 +4932,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> * This is an exception to the general rule that mode_set doesn't turn
> * things on.
> */
> - if (is_lvds) {
> - temp = I915_READ(PCH_LVDS);
> - temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
> - if (HAS_PCH_CPT(dev)) {
> - temp &= ~PORT_TRANS_SEL_MASK;
> - temp |= PORT_TRANS_SEL_CPT(pipe);
> - } else {
> - if (pipe == 1)
> - temp |= LVDS_PIPEB_SELECT;
> - else
> - temp &= ~LVDS_PIPEB_SELECT;
> - }
> -
> - /* set the corresponsding LVDS_BORDER bit */
> - temp |= dev_priv->lvds_border_bits;
> - /* Set the B0-B3 data pairs corresponding to whether we're going to
> - * set the DPLLs for dual-channel mode or not.
> - */
> - if (clock.p2 == 7)
> - temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
> - else
> - temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
> -
> - /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
> - * appropriately here, but we need to look more thoroughly into how
> - * panels behave in the two modes.
> - */
> - temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
> - if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
> - temp |= LVDS_HSYNC_POLARITY;
> - if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
> - temp |= LVDS_VSYNC_POLARITY;
> - I915_WRITE(PCH_LVDS, temp);
> - }
> + if (is_lvds)
> + ironlake_lvds_port_enable(intel_crtc, adjusted_mode, clock.p2);
>
> if (is_dp && !is_cpu_edp) {
> intel_dp_set_m_n(crtc, mode, adjusted_mode);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 4f2b2d6..0b71f6c 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -412,6 +412,9 @@ extern void intel_mark_idle(struct drm_device *dev);
> extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
> extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
> extern bool intel_lvds_init(struct drm_device *dev);
> +extern void ironlake_lvds_port_enable(struct intel_crtc *intel_crtc,
> + struct drm_display_mode *adjusted_mode,
> + int clock_p2);
> extern void intel_dp_init(struct drm_device *dev, int output_reg,
> enum port port);
> void
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 5646895..e418d95 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -587,6 +587,49 @@ static int intel_lvds_set_property(struct drm_connector *connector,
> return 0;
> }
>
> +void ironlake_lvds_port_enable(struct intel_crtc *intel_crtc,
> + struct drm_display_mode *adjusted_mode,
> + int clock_p2)
> +{
> + struct drm_device *dev = intel_crtc->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + enum pipe pipe = intel_crtc->pipe;
> + uint32_t temp;
> +
> + temp = I915_READ(PCH_LVDS);
> + temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
> + if (HAS_PCH_CPT(dev)) {
> + temp &= ~PORT_TRANS_SEL_MASK;
> + temp |= PORT_TRANS_SEL_CPT(pipe);
> + } else {
> + if (pipe == 1)
> + temp |= LVDS_PIPEB_SELECT;
> + else
> + temp &= ~LVDS_PIPEB_SELECT;
> + }
> +
> + /* set the corresponsding LVDS_BORDER bit */
> + temp |= dev_priv->lvds_border_bits;
> + /* Set the B0-B3 data pairs corresponding to whether we're going to
> + * set the DPLLs for dual-channel mode or not.
> + */
> + if (clock_p2 == 7)
> + temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
> + else
> + temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
> +
> + /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
> + * appropriately here, but we need to look more thoroughly into how
> + * panels behave in the two modes.
> + */
> + temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
> + if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
> + temp |= LVDS_HSYNC_POLARITY;
> + if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
> + temp |= LVDS_VSYNC_POLARITY;
> + I915_WRITE(PCH_LVDS, temp);
> +}
> +
> static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
> .mode_fixup = intel_lvds_mode_fixup,
> .mode_set = intel_lvds_mode_set,
> --
> 1.7.10.4
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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