[Intel-gfx] [PATCH] drm/i915: ioremap the right range for the registers on gen2

[Chris Wilson]

Fixes regression from commit 1ca673954355eb4105ef7fccdd770e69d4d3d1ef
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Fri Sep 14 11:57:46 2012 +0100

    drm/i915: Limit the ioremap of the PCI bar to the registers

which only mapped 64k of the register BAR when the full 512k was
required.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_dma.c |   14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index f0cad84..5779e8f 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1524,13 +1524,15 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 		dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 
-	/* Restrict iomap to avoid clobbering the GTT which we want WC mapped.
-	 * Do not attempt to map the whole BAR!
-	 */
 	mmio_bar = IS_GEN2(dev) ? 1 : 0;
-	if (info->gen < 3)
-		mmio_size = 64*1024;
-	else if (info->gen < 5)
+	/* Before gen4, the registers and the GTT are behind different BARs.
+	 * However, from gen4 onwards, the registers and the GTT are shared
+	 * in the same BAR, so we want to restrict this ioremap from
+	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
+	 * the register BAR remains the same size for all the earlier
+	 * generations up to Ironlake.
+	 */
+	if (info->gen < 5)
 		mmio_size = 512*1024;
 	else
 		mmio_size = 2*1024*1024;
-- 
1.7.10.4