[Intel-gfx] [PATCH 5/9] drm/i915: Fix lanecontrol, vswing, preemp for Valleyview DisplayPort
Daniel Vetter
daniel at ffwll.ch
Wed Sep 26 16:24:59 CEST 2012
On Wed, Sep 26, 2012 at 07:07:34PM +0530, Vijay Purushothaman wrote:
> In Valleyview voltage swing, pre-emphasis and lane control registers can
> be programmed only through the h/w side band fabric. Also use
> i9xx_update_pll to program the correct DPLL sequence.
>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman at intel.com>
> Signed-off-by: Gajanan Bhat <gajanan.bhat at intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
> ---
> drivers/gpu/drm/i915/intel_crt.c | 7 ++++++
> drivers/gpu/drm/i915/intel_display.c | 44 ++++++++++++++++++++++++++++------
> 2 files changed, 44 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index c42b980..bd23bdf 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -308,6 +308,13 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
> bool ret;
> u32 save_adpa;
>
> + /*
> + * Disable crt detect hotplug for VLV X0. spurious hot plug
> + * detect calls crashes the X0 system
> + */
> + if (IS_VALLEYVIEW(dev))
> + return false;
This hunk here belongs into a different patch.
> +
> save_adpa = adpa = I915_READ(ADPA);
> DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 68828e7..a8a81d1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3944,6 +3944,10 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
> int pipe = intel_crtc->pipe;
> u32 fp, fp2 = 0;
>
> + /* Disable FP0 register programming for VLV X0 */
> + if (IS_VALLEYVIEW(dev))
> + return;
This patch folds back the vlv_update_pll function into the i9xx_update_pll
function, which is imo the wrong approach (since you add quite some if
(IS_VLV) blocks). Better would be to move the i9xx_update_pll_dividers
into i8xx_update_pll and i9xx_update_pll and then keep the vlv_update_pll
(and only apply the necessary fixes there.
-Daniel
)
> +
> if (IS_PINEVIEW(dev)) {
> fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
> if (reduced_clock)
> @@ -4051,12 +4055,13 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>
> intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
>
> - pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
> + pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
> (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
> - (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
> + (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
> + (5 << DPIO_CLK_BIAS_CTL_SHIFT);
> intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
>
> - intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
> + intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
>
> dpll |= DPLL_VCO_ENABLE;
> I915_WRITE(DPLL(pipe), dpll);
> @@ -4076,7 +4081,7 @@ static void vlv_update_pll(struct drm_crtc *crtc,
> POSTING_READ(DPLL_MD(pipe));
> }
>
> - intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
> + intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
> }
>
> static void i9xx_update_pll(struct drm_crtc *crtc,
> @@ -4112,6 +4117,12 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
> if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> dpll |= DPLL_DVO_HIGH_SPEED;
>
> + if (IS_VALLEYVIEW(dev)) {
> + dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
> + dpll |= DPLL_REFA_CLK_ENABLE_VLV;
> + dpll |= DPLL_INTEGRATED_CLOCK_VLV;
> + }
> +
> /* compute bitmask from p1 value */
> if (IS_PINEVIEW(dev))
> dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
> @@ -4152,6 +4163,17 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
> dpll |= DPLL_VCO_ENABLE;
> I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> POSTING_READ(DPLL(pipe));
> +
> + /*
> + * In Valleyview PLL and program lane counter registes are exposed
> + * through DPIO interface
> + */
> + if (IS_VALLEYVIEW(dev)) {
> + int refclk;
> + refclk = i9xx_get_refclk(crtc, num_connectors);
> + vlv_update_pll(crtc, mode, adjusted_mode, clock, NULL, refclk,
> + num_connectors);
> + }
> udelay(150);
>
> /* The LVDS pin pair needs to be on before the DPLLs are enabled.
> @@ -4170,6 +4192,17 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
> POSTING_READ(DPLL(pipe));
> udelay(150);
>
> + /* Now program lane control registers for Valleyview */
> + if (IS_VALLEYVIEW(dev)) {
> + u32 temp = 0;
> + temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(pipe));
> + temp |= (1 << 20);
> + intel_dpio_write(dev_priv, DPIO_DATA_LANE_A(pipe), temp);
> + temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_B(pipe));
> + temp |= (1 << 20);
> + intel_dpio_write(dev_priv, DPIO_DATA_LANE_B(pipe), temp);
> + }
> +
> if (INTEL_INFO(dev)->gen >= 4) {
> u32 temp = 0;
> if (is_sdvo) {
> @@ -4332,9 +4365,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>
> if (IS_GEN2(dev))
> i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
> - else if (IS_VALLEYVIEW(dev))
> - vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
> - refclk, num_connectors);
> else
> i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
> has_reduced_clock ? &reduced_clock : NULL,
> --
> 1.7.9.5
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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