[Intel-gfx] [PATCH 6/9] drm/i915: Add eDP support for Valleyview

[Jani Nikula]

On Wed, 26 Sep 2012, Daniel Vetter <daniel at ffwll.ch> wrote:
> On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index a8a81d1..aee6151 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4405,6 +4405,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>>  		}
>>  	}
>>  
>> +	if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
>> +		pipeconf |= PIPECONF_BPP_6 |
>> +			PIPECONF_ENABLE |
>> +			I965_PIPECONF_ACTIVE;
>> +	}
>
> No.
>
> Jani Nikula and me just figured out that we have a giant mess with 6bpc
> dithering on DP outputs, but unconditionally enabling 6bpc on vlv eDP only
> papers over issues.

Vijay, please check commit 0c96c65b in drm-intel-fixes.

BR,
Jani.