[Intel-gfx] [PATCH v2 2/9] drm/i915: Fix SDVO IER and status bits for Valleyview

Jesse Barnes jbarnes at virtuousgeek.org
Thu Sep 27 17:13:26 CEST 2012


On Thu, 27 Sep 2012 19:13:02 +0530
Vijay Purushothaman <vijay.a.purushothaman at intel.com> wrote:

> Fixed SDVOB and SDVOC bit definitions for Valleyview.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman at intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c |    6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d915126..1a974d9 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2020,7 +2020,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
>  #endif
>  
>  	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
> -#if 0 /* FIXME: check register definitions; some have moved */
>  	/* Note HDMI and DP share bits */
>  	if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
>  		hotplug_en |= HDMIB_HOTPLUG_INT_EN;
> @@ -2028,15 +2027,14 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
>  		hotplug_en |= HDMIC_HOTPLUG_INT_EN;
>  	if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
>  		hotplug_en |= HDMID_HOTPLUG_INT_EN;
> -	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
> +	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
>  		hotplug_en |= SDVOC_HOTPLUG_INT_EN;
> -	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
> +	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
>  		hotplug_en |= SDVOB_HOTPLUG_INT_EN;
>  	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
>  		hotplug_en |= CRT_HOTPLUG_INT_EN;
>  		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
>  	}
> -#endif
>  
>  	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
>  

Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center



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