[Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

[Daniel Vetter]

On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter <daniel at ffwll.ch> wrote:
> So I've checked hsw bspec and the problem is that hw guys again
> changed the bits around a bit, and I think on HSW we actually want
> (0x8 << 3) instead of what's currently there.

Meh, I've screwed up reading the tables, 0x3 << 3 is what we imo want,
so nothing needs to be changed. Sorry for the confusion.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch