[Intel-gfx] [PATCH] tests/kms_flip: don't leak gpu hang state

Daniel Vetter daniel.vetter at ffwll.ch
Mon Apr 8 09:21:51 CEST 2013


We need to clear out the error_state. While at it also make sure that
the hang was indeed detected.

Whoever writes the next test to race against gpu hangs should probably
extract these two functions into the drmtest library. Which just one
user that's not really worth it right now.

v2: Fill cpu caches with data for each newly allocated bo. This seems
to do the trick on my snb here _really_ reliably. So apparently the
backsnoop for llc gtt writes is the crucial ingredient here to make
the test fail.

While at it, also stop leaking mmap space.

Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 tests/gem_fence_thrash.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/tests/gem_fence_thrash.c b/tests/gem_fence_thrash.c
index 3fc72a1..01fd0f6 100644
--- a/tests/gem_fence_thrash.c
+++ b/tests/gem_fence_thrash.c
@@ -69,6 +69,12 @@ bo_create (int fd, int tiling)
 
 	handle = gem_create(fd, OBJECT_SIZE);
 
+	/* dirty cpu caches a bit ... */
+	ptr = gem_mmap__cpu(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
+	assert(ptr);
+	memset(ptr, 0, OBJECT_SIZE);
+	munmap(ptr, OBJECT_SIZE);
+
 	gem_set_tiling(fd, handle, tiling, 1024);
 
 	ptr = gem_mmap(fd, handle, OBJECT_SIZE, PROT_READ | PROT_WRITE);
@@ -104,7 +110,7 @@ _bo_write_verify(struct test *t)
 {
 	int fd = t->fd;
 	int i, k;
-	volatile uint32_t **s;
+	uint32_t **s;
 	uint32_t v;
 	unsigned int dwords = OBJECT_SIZE >> 2;
 	const char *tile_str[] = { "none", "x", "y" };
@@ -141,6 +147,9 @@ _bo_write_verify(struct test *t)
 		}
 	}
 
+	for (k = 0; k < t->num_surfaces; k++)
+		munmap(s[k], OBJECT_SIZE);
+
 	free(s);
 }
 
@@ -216,11 +225,19 @@ main(int argc, char **argv)
 	if (drmtest_run_subtest("bo-write-verify-threaded-none"))
 		assert (run_test(5, bo_write_verify, I915_TILING_NONE, 2) == 0);
 
-	if (drmtest_run_subtest("bo-write-verify-threaded-x"))
+	if (drmtest_run_subtest("bo-write-verify-threaded-x")) {
+		assert (run_test(2, bo_write_verify, I915_TILING_X, 2) == 0);
 		assert (run_test(5, bo_write_verify, I915_TILING_X, 2) == 0);
+		assert (run_test(10, bo_write_verify, I915_TILING_X, 2) == 0);
+		assert (run_test(20, bo_write_verify, I915_TILING_X, 2) == 0);
+	}
 
-	if (drmtest_run_subtest("bo-write-verify-threaded-y"))
+	if (drmtest_run_subtest("bo-write-verify-threaded-y")) {
+		assert (run_test(2, bo_write_verify, I915_TILING_Y, 2) == 0);
 		assert (run_test(5, bo_write_verify, I915_TILING_Y, 2) == 0);
+		assert (run_test(10, bo_write_verify, I915_TILING_Y, 2) == 0);
+		assert (run_test(20, bo_write_verify, I915_TILING_Y, 2) == 0);
+	}
 
 	if (drmtest_run_subtest("bo-copy"))
 		assert(run_test(1, bo_copy, I915_TILING_X, 1) == 0);
-- 
1.7.11.7




More information about the Intel-gfx mailing list