[Intel-gfx] [PATCH] drm/i915: use lower aux clock divider on non-ULT HSW

[Paulo Zanoni]

Hi

2013/4/8 Jani Nikula <jani.nikula at intel.com>:
> Workaround to avoid intermittent aux channel failures, per spec change.
>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
>
> ---
>
> Untested.
> ---
>  drivers/gpu/drm/i915/intel_dp.c |    5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 482b5e5..5fec183 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -344,7 +344,10 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>          * Note that PCH attached eDP panels should use a 125MHz input
>          * clock divider.
>          */
> -       if (is_cpu_edp(intel_dp)) {
> +       if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> +               /* Workaround for non-ULT HSW */
> +               aux_clock_divider = 74;
> +       } else if (is_cpu_edp(intel_dp)) {

Your patch will affect the CPU DP AUX too, but it should only affect
the PCH DP AUX registers. You should move this to the !is_cpu_edp
case.

>                 if (HAS_DDI(dev))
>                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
>                 else if (IS_VALLEYVIEW(dev))
> --
> 1.7.10.4
>
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--
Paulo Zanoni