[Intel-gfx] [PATCH 03/10] drm/i915: Map registers before GTT init

[Daniel Vetter]

On Mon, Apr 08, 2013 at 06:43:49PM -0700, Ben Widawsky wrote:
> This will allow us to read/write registers in GTT init.
> 
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 48 ++++++++++++++++++++---------------------
>  1 file changed, 24 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 4a1a517..ad7f284 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1518,6 +1518,28 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>  		goto free_priv;
>  	}
>  
> +	mmio_bar = IS_GEN2(dev) ? 1 : 0;
> +	/* Before gen4, the registers and the GTT are behind different BARs.
> +	 * However, from gen4 onwards, the registers and the GTT are shared
> +	 * in the same BAR, so we want to restrict this ioremap from
> +	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
> +	 * the register BAR remains the same size for all the earlier
> +	 * generations up to Ironlake.
> +	 */
> +	if (info->gen < 5)
> +		mmio_size = 512*1024;
> +	else
> +		mmio_size = 2*1024*1024;
> +
> +	dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
> +	if (!dev_priv->regs) {
> +		DRM_ERROR("failed to map registers\n");
> +		ret = -EIO;
> +		goto put_gmch;

goto put_bridge is what I've fixed up here.

Queued for -next, thanks for the patch.
-Daniel

> +	}
> +
> +	intel_early_sanitize_regs(dev);
> +
>  	ret = i915_gem_gtt_init(dev);
>  	if (ret)
>  		goto put_bridge;
> @@ -1542,28 +1564,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>  	if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
>  		dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
>  
> -	mmio_bar = IS_GEN2(dev) ? 1 : 0;
> -	/* Before gen4, the registers and the GTT are behind different BARs.
> -	 * However, from gen4 onwards, the registers and the GTT are shared
> -	 * in the same BAR, so we want to restrict this ioremap from
> -	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
> -	 * the register BAR remains the same size for all the earlier
> -	 * generations up to Ironlake.
> -	 */
> -	if (info->gen < 5)
> -		mmio_size = 512*1024;
> -	else
> -		mmio_size = 2*1024*1024;
> -
> -	dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
> -	if (!dev_priv->regs) {
> -		DRM_ERROR("failed to map registers\n");
> -		ret = -EIO;
> -		goto put_gmch;
> -	}
> -
> -	intel_early_sanitize_regs(dev);
> -
>  	aperture_size = dev_priv->gtt.mappable_end;
>  
>  	dev_priv->gtt.mappable =
> @@ -1686,10 +1686,10 @@ out_mtrrfree:
>  		dev_priv->mm.gtt_mtrr = -1;
>  	}
>  	io_mapping_free(dev_priv->gtt.mappable);
> -out_rmmap:
> -	pci_iounmap(dev->pdev, dev_priv->regs);
>  put_gmch:
>  	dev_priv->gtt.gtt_remove(dev);
> +out_rmmap:
> +	pci_iounmap(dev->pdev, dev_priv->regs);
>  put_bridge:
>  	pci_dev_put(dev_priv->bridge_dev);
>  free_priv:
> -- 
> 1.8.2.1
> 
> _______________________________________________
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> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch