[Intel-gfx] [PATCH 2/2] drm/i915: Increase max fence pitch limit to 256KB on IVB+

[Daniel Vetter]

On Tue, Apr 09, 2013 at 03:03:28PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 09, 2013 at 01:54:01PM +0200, Daniel Vetter wrote:
> > On Tue, Apr 09, 2013 at 11:45:05AM +0300, ville.syrjala at linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > 
> > > BSpec contains several scattered notes which state that the maximum
> > > fence stride was increased to 256KB on IVB.
> > > 
> > > Testing on real hardware agrees.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_gem_tiling.c | 9 ++++++---
> > >  drivers/gpu/drm/i915/i915_reg.h        | 1 +
> > >  2 files changed, 7 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> > > index c807eb9..139d17d 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> > > @@ -217,9 +217,12 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> > >  		tile_width = 512;
> > >  
> > >  	/* check maximum stride & object size */
> > > -	if (INTEL_INFO(dev)->gen >= 4) {
> > > -		/* i965 stores the end address of the gtt mapping in the fence
> > > -		 * reg, so dont bother to check the size */
> > > +	/* i965+ stores the end address of the gtt mapping in the fence
> > > +	 * reg, so dont bother to check the size */
> > > +	if (INTEL_INFO(dev)->gen >= 7) {
> > 
> > I've thought that his does not apply to vlv? Or has that now changed?
> 
> The docs are telling me that VLV also has 256KB max stride.

Queued for -next, thanks for the patch.
-Daniel

> 
> > -Daniel
> > 
> > > +		if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
> > > +			return false;
> > > +	} else if (INTEL_INFO(dev)->gen >= 4) {
> > >  		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
> > >  			return false;
> > >  	} else {
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 0e4b7fb..ec4e054 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -424,6 +424,7 @@
> > >  
> > >  #define FENCE_REG_SANDYBRIDGE_0		0x100000
> > >  #define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32
> > > +#define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
> > >  
> > >  /* control register for cpu gtt access */
> > >  #define TILECTL				0x101000
> > > -- 
> > > 1.8.1.5
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx at lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch