[Intel-gfx] [PATCH] drm/i915: Enable FBC at Haswell.

[Ville Syrjälä]

On Tue, Apr 16, 2013 at 01:33:44PM -0300, Rodrigo Vivi wrote:
> This patch introduce Frame Buffer Compression (FBC) support for HSW.
> It adds a new function haswell_enable_fbc to avoid getting
> ironlake_enable_fbc messed with many IS_HASWELL checks.
> 
> v2: Fixes from Ville.
>      	*  Fix Plane. FBC is tied to primary plane A in HSW
>     	*  Fix DPFC initial write to avoid let trash on the register.
> 
> v3: Checking for bad plane on intel_update_fbc() as Chris suggested.
> 
> v4: Ville pointed out that according to BSpec FBC_CTL bits 0:3 must be 0.
> 
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |  1 +
>  drivers/gpu/drm/i915/i915_reg.h |  6 ++++++
>  drivers/gpu/drm/i915/intel_pm.c | 42 +++++++++++++++++++++++++++++++++++++++--
>  3 files changed, 47 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 9ebe895..ba0935d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -314,6 +314,7 @@ static const struct intel_device_info intel_haswell_m_info = {
>  	GEN7_FEATURES,
>  	.is_haswell = 1,
>  	.is_mobile = 1,
> +	.has_fbc = 1,
>  };
>  
>  static const struct pci_device_id pciidlist[] = {		/* aka */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 077d40f..b9725ba 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -857,6 +857,12 @@
>  #define   SNB_CPU_FENCE_ENABLE	(1<<29)
>  #define DPFC_CPU_FENCE_OFFSET	0x100104
>  
> +/* Framebuffer compression for Haswell */
> +#define HSW_FBC_RT_BASE			0x7020
> +#define   HSW_FBC_RT_BASE_ADDR_SHIFT	12
> +
> +#define   HSW_DPFC_CTL_FENCE_EN		(1<<28)
> +#define   HSW_DPFC_CTL_DISABLE_SLB_INIT	(1<<15)

These registers/bits already exists on IVB. All the registers you set
seem to be in line with IVB BSpec, so I think you just need to to
s/haswell/gen7/ everywhere, and then we get FBC for IVB for free.

Well, the only real work left would be adding plane B and C FBC
support on IVB.

The new DPFC_CTL bits should also probably be grouped with the rest of
the ILK_DPFC_CONTROL bits, otherwise it's difficult to know which
register they belong to.

>  
>  /*
>   * GPIO regs
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f747cb0..7b20fc5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -253,6 +253,38 @@ static bool ironlake_fbc_enabled(struct drm_device *dev)
>  	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
>  }
>  
> +static void haswell_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_framebuffer *fb = crtc->fb;
> +	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> +	struct drm_i915_gem_object *obj = intel_fb->obj;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	unsigned long stall_watermark = 200;
> +
> +	I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
> +		   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
> +		   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
> +	I915_WRITE(HSW_FBC_RT_BASE,
> +		   obj->gtt_offset << HSW_FBC_RT_BASE_ADDR_SHIFT |
> +		   ILK_FBC_RT_VALID);
> +
> +	I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
> +		   HSW_DPFC_CTL_FENCE_EN | HSW_DPFC_CTL_DISABLE_SLB_INIT);
> +
> +	if (obj->fence_reg != I915_FENCE_REG_NONE) {

Is there actually a case that we wouldn't have a fence? I think we
always reserve a fence for scanout even though we wouldn't really
need it on gen4+ (or for untiled on gen2-3). At least we don't have any
sanity checks for fence_reg in the ironlake_enable_fbc().

But if this can happen, then shouldn't we also clear the
"fence enable" bit from ILK_DPFC_CONTROL?

> +		I915_WRITE(SNB_DPFC_CTL_SA,
> +			   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
> +		I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
> +	} else
> +		I915_WRITE(SNB_DPFC_CTL_SA, ~SNB_CPU_FENCE_ENABLE);
> +
> +	sandybridge_blit_fbc_update(dev);
> +
> +	DRM_DEBUG_KMS("enabled fbc on plane A\n");
> +}
> +
>  bool intel_fbc_enabled(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -460,7 +492,8 @@ void intel_update_fbc(struct drm_device *dev)
>  		dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
>  		goto out_disable;
>  	}
> -	if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
> +	if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev))
> +	    && intel_crtc->plane != 0) {
>  		DRM_DEBUG_KMS("plane not 0, disabling compression\n");
>  		dev_priv->no_fbc_reason = FBC_BAD_PLANE;
>  		goto out_disable;
> @@ -4180,7 +4213,12 @@ void intel_init_pm(struct drm_device *dev)
>  	if (I915_HAS_FBC(dev)) {
>  		if (HAS_PCH_SPLIT(dev)) {
>  			dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
> -			dev_priv->display.enable_fbc = ironlake_enable_fbc;
> +			if (IS_HASWELL(dev))
> +				dev_priv->display.enable_fbc =
> +					haswell_enable_fbc;
> +			else
> +				dev_priv->display.enable_fbc =
> +					ironlake_enable_fbc;
>  			dev_priv->display.disable_fbc = ironlake_disable_fbc;
>  		} else if (IS_GM45(dev)) {
>  			dev_priv->display.fbc_enabled = g4x_fbc_enabled;
> -- 
> 1.8.1.4

-- 
Ville Syrjälä
Intel OTC