[Intel-gfx] [PATCH 2/4] drm/i915: Clarify DSPPOS/DSPSIZE and pipe selection for planes A/B

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

DSPPOS/DSPSIZE for planes A/B doesn't exist on Gen4+, so don't write
them.

Also the pipe selection for planes A and B is only relevant for Gen3
and earlier. Gen4 moved to fixed plane<->pipe mapping. Plane C is
still movable between pipes on Gen4, but that fact is not relevant
for the CRTC codepaths since we never use plane C as the CRTC plane.

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fb88356..4f4a8d1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4719,8 +4719,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	/* Set up the display plane register */
 	dspcntr = DISPPLANE_GAMMA_ENABLE;
 
-	if (!IS_VALLEYVIEW(dev)) {
-		if (pipe == 0)
+	/* planes A/B are fixed to pipes A/B respectively on Gen4+ */
+	if (INTEL_INFO(dev)->gen <= 3) {
+		if (pipe == PIPE_A)
 			dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
 		else
 			dspcntr |= DISPPLANE_SEL_PIPE_B;
@@ -4733,11 +4734,15 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 
 	/* pipesrc and dspsize control the size that is scaled from,
 	 * which should always be the user's requested size.
+	 *
+	 * DSPPOS/DSPSIZE for planes A/B only exist on Gen3 and earlier.
 	 */
-	I915_WRITE(DSPSIZE(plane),
-		   ((mode->vdisplay - 1) << 16) |
-		   (mode->hdisplay - 1));
-	I915_WRITE(DSPPOS(plane), 0);
+	if (INTEL_INFO(dev)->gen <= 3) {
+		I915_WRITE(DSPSIZE(plane),
+			   ((mode->vdisplay - 1) << 16) |
+			   (mode->hdisplay - 1));
+		I915_WRITE(DSPPOS(plane), 0);
+	}
 
 	i9xx_set_pipeconf(intel_crtc);
 
-- 
1.8.1.5