[Intel-gfx] [PATCH 1/8] drm/i915: update VLV PLL and DPIO code v10

[Daniel Vetter]

On Thu, Apr 18, 2013 at 10:46:08AM +0200, Daniel Vetter wrote:
> @@ -3782,6 +3905,27 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
>  
>  	i9xx_pfit_disable(intel_crtc);
>  
> +	for_each_encoder_on_crtc(dev, crtc, encoder)
> +		if (encoder->post_disable)
> +			encoder->post_disable(encoder);
> +
> +	/* Reset lane for VLV platform*/
> +	if (IS_VALLEYVIEW(dev)) {
> +		mutex_lock(&dev_priv->dpio_lock);
> +		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
> +			intel_dpio_write(dev_priv, DPIO_PCS_TX(0),
> +					 0x00000000);
> +			intel_dpio_write(dev_priv, DPIO_PCS_CLK(0),
> +					 0x00e00060);
> +		} else {
> +			intel_dpio_write(dev_priv, DPIO_PCS_TX(1),
> +					 0x00000000);
> +			intel_dpio_write(dev_priv, DPIO_PCS_CLK(1),
> +					 0x00e00060);
> +		}
> +		mutex_unlock(&dev_priv->dpio_lock);
> +	}
> +

Oops, I've missed this part here in my split-out. Probably needs the same
port abstraction like the enable code (i.e. DP seems to be on the wrong
port) and then shovelled into ->post_disable.
-Daniel

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch