[Intel-gfx] [PATCH 2/6] drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue

[Rodrigo Vivi]

Display register 42000h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 86a941a..6315627 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -270,6 +270,8 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 		   IVB_DPFC_CTL_FENCE_EN |
 		   intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 
+	/* WaFbcAsynchFlipDisableFbcQueue */
+	I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 	I915_WRITE(SNB_DPFC_CTL_SA,
 		   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 	I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
-- 
1.8.1.4