[Intel-gfx] [PATCH 3/6] drm/i915: IVB FBC WaFbcDisableDpfcClockGating

[Rodrigo Vivi]

Display register 42020h bit 9 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6315627..a33490c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -242,6 +242,11 @@ static void ironlake_disable_fbc(struct drm_device *dev)
 		dpfc_ctl &= ~DPFC_CTL_EN;
 		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 
+		if (IS_IVYBRIDGE(dev))
+			/* WaFbcDisableDpfcClockGating */
+			I915_WRITE(ILK_DSPCLK_GATE_D,
+				   ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
+
 		DRM_DEBUG_KMS("disabled FBC\n");
 	}
 }
@@ -272,6 +277,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 
 	/* WaFbcAsynchFlipDisableFbcQueue */
 	I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
+	/* WaFbcDisableDpfcClockGating */
+	I915_WRITE(ILK_DSPCLK_GATE_D, ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
+
 	I915_WRITE(SNB_DPFC_CTL_SA,
 		   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 	I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
-- 
1.8.1.4