[Intel-gfx] [PATCH 07/15] drm/i915: Fixup non-24bpp support for VGA screens on Haswell

[Ville Syrjälä]

On Fri, Apr 19, 2013 at 11:24:39AM +0200, Daniel Vetter wrote:
> The LPT PCH only supports 8bpc, so we need to force the pipe bpp
> to the right value.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_crt.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 58b4a53..1b9ebf4 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -207,6 +207,10 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
>  	if (HAS_PCH_SPLIT(dev))
>  		pipe_config->has_pch_encoder = true;
>  
> +	/* LPT FDI RX only supports 8bpc. */
> +	if (HAS_PCH_LPT(dev))
> +		pipe_config->pipe_bpp = 24;
> +
>  	return true;
>  }
>  
> -- 
> 1.7.11.7
> 
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-- 
Ville Syrjälä
Intel OTC