[Intel-gfx] [PATCH 4/6] drm/i915: Enable FBC at Haswell.

[Ville Syrjälä]

On Tue, Apr 23, 2013 at 02:52:19PM -0300, Rodrigo Vivi wrote:
> This patch introduce Frame Buffer Compression (FBC) support for HSW.
> FBC is tied to primary plane A in HSW.

The docs say FBC must be disabled before disabling the plane on HSW.
We're doing these steps in the opposite order on ILK+. Although maybe
it's not a big deal when were disabling the pipe too.

But I'd just change the order of these operations in both
ironlake_crtc_disable() and haswell_crtc_disable(). Otherwise people
will get confused every time they try to figure out why the order of
operations is different.

> ---
>  drivers/gpu/drm/i915/i915_drv.c |  1 +
>  drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++------
>  2 files changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index a073b4c..6bf7ab4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -315,6 +315,7 @@ static const struct intel_device_info intel_haswell_m_info = {
>  	GEN7_FEATURES,
>  	.is_haswell = 1,
>  	.is_mobile = 1,
> +	.has_fbc = 1,
>  };
>  
>  static const struct pci_device_id pciidlist[] = {		/* aka */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a33490c..972a1a3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -275,10 +275,12 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
>  		   IVB_DPFC_CTL_FENCE_EN |
>  		   intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
>  
> -	/* WaFbcAsynchFlipDisableFbcQueue */
> -	I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
> -	/* WaFbcDisableDpfcClockGating */
> -	I915_WRITE(ILK_DSPCLK_GATE_D, ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
> +	if (IS_IVYBRIDGE(dev)) {
> +		/* WaFbcAsynchFlipDisableFbcQueue */
> +		I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
> +		/* WaFbcDisableDpfcClockGating */
> +		I915_WRITE(ILK_DSPCLK_GATE_D, ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
> +	}
>  
>  	I915_WRITE(SNB_DPFC_CTL_SA,
>  		   SNB_CPU_FENCE_ENABLE | obj->fence_reg);
> @@ -496,7 +498,8 @@ void intel_update_fbc(struct drm_device *dev)
>  		dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
>  		goto out_disable;
>  	}
> -	if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
> +	if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
> +	    intel_crtc->plane != 0) {
>  		DRM_DEBUG_KMS("plane not 0, disabling compression\n");
>  		dev_priv->no_fbc_reason = FBC_BAD_PLANE;
>  		goto out_disable;
> @@ -4216,7 +4219,7 @@ void intel_init_pm(struct drm_device *dev)
>  	if (I915_HAS_FBC(dev)) {
>  		if (HAS_PCH_SPLIT(dev)) {
>  			dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
> -			if (IS_IVYBRIDGE(dev))
> +			if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
>  				dev_priv->display.enable_fbc =
>  					gen7_enable_fbc;
>  			else
> -- 
> 1.8.1.4
> 
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-- 
Ville Syrjälä
Intel OTC